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TPS23757
www.ti.com
SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
If V VDD - V VSS drops below the lower PoE UVLO (V UVLO-R – V UVLO-H , ~30.5 V), the hotswap MOSFET is turned off,
but the converter will still run. The converter will stop if V VC falls below the converter UVLO (V CUV – V CUVH ,
~5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by V CTL (V CTL < V ZDC , ~1.5 V), or the
converter is in thermal shutdown.
PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current vs.
time template with specified minimum and maximum sourcing boundaries. The peak output current may be as
high as 50 A for 10 μ s or 1.75 A for 75 ms. This makes robust protection of the PD device even more important
than it was in IEEE 802.3-2008.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V RTN -
V VSS rising as a result. If V RTN rises above ~12 V for longer than ~400 μ s, the current limit reverts to the inrush
value, and turns the converter off. The 400 μ s deglitch feature prevents momentary transients from causing a PD
reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 22 shows an
example of recovery from a 14 V PSE rising voltage step. The hotswap MOSFET goes into current limit,
overshooting to a relatively low current, recovers to ~450 mA full current limit, and charges the input capacitor
while the converter continues to run. The MOSFET did not go into foldback because V RTN – V VSS was below 12
V after the 400 μ s deglitch.
I PI
200 mA/div
10 V/div
20 V/div
V RTN - V VSS
V VDD - V VSS
11.8 V at 400 ms
14 V Input Step
C IN Completes Charge
While Converter Operates
t - Time - 500 m s/div
Figure 22. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or
operation into a V DD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The
hotswap MOSFET will be re-enabled with the inrush current limit when exiting from an overtemperature event.
Pulling DEN to V SS during powered operation causes the internal hotswap MOSFET to turn OFF. This feature
allows a PD with Option three ORing per Figure 23 to achieve adapter priority. Care must be taken with
synchronous converter topologies that can deliver power in both directions.
The hotswap switch will be forced off under the following conditions:
1. V APD above V APDEN (~1.5 V)
2. V DEN < V PD-DIS when V VDD – V VSS is in the operational range
3. PD overtemperature
4. (V VDD – V VSS ) < PoE UVLO (~30.5 V).
Copyright ? 2009–2013, Texas Instruments Incorporated
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